This application relies for priority upon Korean Patent Application No. 2002-0005422, filed on Jan. 30, 2002, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to semiconductor integrated circuit devices and, more particularly, to a semiconductor memory device that internally generates a test clock signal having a shorter cycle than an external clock cycle and uses the test clock signal to apply a stress to components (e.g., memory cells) more efficiently.
With the advance in CMOS integration circuit technologies, the integration level and operating speed of semiconductor devices has become very high. Thus, a wafer-level test apparatus should test semiconductor devices at a high frequency. However, since current wafer-level test apparatuses cannot support a high frequency or operating speed, technologies for performing a wafer test operation at a higher frequency have been required in order to test semiconductor devices (e.g., semiconductor memory devices) operating at a high frequency. There have been suggested technologies that internally generate an internal clock signal having a short cycle of an operation frequency for normal read and write operations to test semiconductor devices at a high frequency.
One such technology is disclosed in U.S. Pat. No. 6,038,181 entitled xe2x80x9cEFFICIENT SEMICONDUCTOR BURN-IN CIRCUIT AND METHOD OF OPERATIONxe2x80x9d, issued to George M. Braceras et. al. on Mar. 14, 2000. FIGS. 1 and 2 of the present application are substantially the same as FIGS. 3 and 4 of the ""181 patent, where FIG. 1 is a block diagram of a conventional semiconductor memory device and FIG. 2 is a timing diagram of the semiconductor memory device shown in FIG. 1.
According to the conventional semiconductor memory device, a memory or logic device under test receives a clock that operates each device under test by way of a plurality of write and read operations during each power cycle. The conventional wafer-level test operation is described more fully in the ""181 patent but need not be explained in further detail.
The above-mentioned semiconductor memory device suffers from several disadvantages as follows.
In order to generate an internal test clock signal, a dummy wordline and a dummy bitline must be formed in a memory cell array independently of usable wordlines and bitlines.
In order to calculate the number of cycles of the internal test clock signal, a counter 38 and a reset circuit 40 are additionally needed. Since the cycles of the internal test clock signal are constant, there is a limit on the number of cycles of an internal test clock signal generated during a high period of an external clock signal.
Further, the number of the cycles of the internal test clock signal must be set by a circuit, such as a JTAG test logic circuit 35 shown in FIG. 1 prior to the test operation.
In a write operation, data to be written in a memory cell array 12 must always be input external to the memory cell array 12.
Since a data verify method is used for each input/output pin after applying a stress to memory cells, each input/output pin needs a compare latching circuit 37. As a result, a chip size is increased.
Finally, if data read out from the memory cell array 12 at a first internal test clock cycle is in error, it is impossible to perform an accurate verify operation.
In an exemplary embodiment, the present invention provides a semiconductor device which internally generates an internal clock signal having an operation frequency with a short cycle for normal read and write operations to perform a test operation at a high frequency.
In an exemplary embodiment, the present invention provides a semiconductor memory device which more efficiently applies a stress to memory cells in a wafer test operation mode.
In an exemplary embodiment, the present invention provides a semiconductor memory device which writes data in memory cells during a wafer test operation mode without receiving external data.
In an exemplary embodiment, the present invention provides a semiconductor memory device which varies the number of cycles of an internal test clock signal.
In an exemplary embodiment, the present invention provides a semiconductor memory device which shortens a test time.
In an exemplary embodiment, the present invention provides a semiconductor memory device including a memory cell array, an address buffer circuit, a clock buffer circuit, a test clock generation circuit, a test clock control circuit, a writer circuit, a read circuit, a first pulse generation circuit, a second pulse generation circuit, and a comparator circuit.
The memory cell array stores data information. The address buffer circuit receives an external address in response to a test clock signal. The clock buffer circuit operates in response to a wafer test flag signal, and receives an external clock signal and generates a test period signal in a wafer test operation mode in response to the external clock signal. The test clock generation circuit generates a test clock signal in response to the test period signal. The test clock signal has a shorter period than that of the external clock signal during a half period of the external clock signal. The test clock control circuit determines whether the cycle number of the test clock signal is equal to the reference cycle number and allows the test clock generation circuit to stop generation of the test clock signal. The test clock control circuit generates test data to be written in the memory cell array. The write circuit writes the test data in an area of the memory cell array addressed by the input address in each cycle of the test clock signal. The read circuit reads the test data from the area of the memory cell array in each cycle of the test clock signal and outputs the read-out test data to data lines. The first latch pulse generation circuit generates first and second latch pulse signals in response to the external clock signal. The second latch pulse generation circuit generates a third latch pulse signal in response to a signal on one of the data lines. The comparator circuit operates in response to the first to third latch pulse signals, and determines whether data bits on the data lines have the same value and outputs a flag signal to an exterior as a determination result.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
FIG. 2 is a timing diagram of the semiconductor memory device shown in FIG. 1.
FIG. 3 is a block diagram of a semiconductor memory device according to an exemplary embodiment of the present invention.
FIG. 4 is a circuit diagram showing an exemplary embodiment of a test clock generation circuit shown in FIG. 3.
FIG. 5 is a circuit diagram showing an exemplary embodiment of a delay circuit shown in FIG. 4.
FIG. 6 is a circuit diagram showing an exemplary embodiment of the test clock generation circuit shown in FIG. 3.
FIG. 7 is a circuit diagram showing an exemplary embodiment of a second latch pulse generation circuit shown in FIG. 3.
FIG. 8 illustrates an exemplary embodiment of a comparing circuit shown in FIG. 3.
FIG. 9 illustrates an exemplary embodiment of a first detector shown in FIG. 8.
FIG. 10A and FIG. 10B are timing diagrams of the semiconductor memory device according to an exemplary embodiment of the present invention.
FIG. 11 is a circuit diagram showing an exemplary embodiment of a first latch pulse generation circuit shown in FIG. 3.
FIG. 12 is a circuit diagram showing an exemplary embodiment of a K_DYN circuit shown in FIG. 11.
FIG. 13 is a circuit diagram showing an exemplary embodiment of a delay chain circuit shown in FIG. 11.
FIG. 14 is a circuit diagram showing an exemplary embodiment of the SBI_clock circuit shown in FIG. 11.
FIG. 15 is a circuit diagram showing an exemplary embodiment of the dynamic logic circuit of FIGS. 12 and/or 14.
FIG. 16 is a timing diagram of the first latch pulse generating circuit of FIG. 11 according to an exemplary embodiment of the present invention.